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STRUCTURE PRODUCT NAME TYPE FEATURES
Silicon Monolithic Integrated Circuit 1ch DCDC Converter Controller IC with Built-in Synchronous Rectifier
BD9160FVM
Output Voltage3.3V, Output Current0.6A High Efficiency and Fast Transient Response
ABSOLUTE MAXIMUM RATINGTa=25
Parameter Vcc Voltage PVcc Voltage EN Voltage SWITH Voltage SW Output Current Power Dissipation 1 Power Dissipation 2 Operating Temperature Range Storage Temperature Range Maximum Junction Temperature
1
Symbol VCC PVCC EN SW, ITH ISW Pd1 Pd2 Topr Tstg Tjmax
Limit -0.3+7 * -0.3+7 * -0.3+7 -0.3+7 1.1 *
1 2 3 1 1
Unit V V V V A mW mW
387.5 * 587.4 *
-25+85 -55+150 +150
* Pd, ASO, and Tjmax=150 should not be exceeded. 2 * Derating is 3.1mW / for temperatures above Ta=25. 3 * Derating is 4.7mW / for temperatures above Ta=25 (when mounted on 70mmx70mmx1.6mm glass epoxy PCB).
OPERATING CONDITIONSTa=-25+85
Parameter Vcc Voltage PVcc Voltage EN Voltage SW Average Output Current * Pd and ASO should not be exceeded.
4
Symbol VCC PVCC EN ISW
Min. 4.5 4.5 0 -
Typ. 5.0 5.0 -
Max. 5.5 5.5 VCC 0.6*
4
Unit V V V A
REV.A
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ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Ta=25 VCC=PVCC=5V, EN=Vcc
Parameter Standby Current Bias Current EN Low Voltage EN High Voltage EN Input Current Oscillation Frequency Pch FET ON Resistance Nch FET ON Resistance Output Voltage ITH SINK Current ITH Source Current UVLO Threshold Voltage UVLO Release Voltage Soft Start Time Timer Latch Time Output Short circuit Threshold Voltage Symbol ISTB ICC VENL VENH IEN FOSC RONP RONN VOUT ITHSI ITHSO VUVLO1 VUVLO2 TSS TLATCH VSCP Limit Min. 2.0 0.8 3.234 10 10 3.6 3.65 0.5 1 1.5 Typ. 0 250 GND Vcc 1 1 0.44 0.33 3.300 20 20 3.8 3.9 1 2 2 Max. 10 400 0.8 10 1.2 0.74 0.53 3.366 4.0 4.2 2 3 2.7 Unit A A V V A MHz V A A V V ms ms V SCP/TSD Operational Mode VOUT=3.3V0V VOUT =3.88V VOUT =2.72V VCC=5V0V VCC=0V5V Stand-by Mode Active Mode VEN=5V Condition EN=GND
PVCC=5V PVCC=5V
PHYSICAL DIMENSION
BLOCK DIAGRAMAPPLICATION CIRCUIT
VCC EN 3 8 PVCC 7 10F Current Comp Current Sense/ Protect + Driver Logic 6 4.7H SW 10F Soft Start UVLO TSD SCP 5 PGND 4 GND 1 VOUT 2 ITH 30k 330pF Output VCC 5V Input
VREF D91 6 0 Lot No. 1PIN MARK
+
RQ S
Gm Amp SLOPE CLK OSC + VCC
MSOP8 (Unit:mm) PIN No. PIN NAME PIN No. PIN Name 1 VOUT 2 ITH 3 EN 4 GND 5 PGND 6 SW 7 PVCC 8 VCC REV. A
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NOTES FOR USE
(1) Absolute maximum rating Although the quality of this IC is rigorously controlled and will function properly in normal operating conditions, the IC may be destroyed when applied voltage or operating temperature exceeds its absolute maximum rating. Because short mode or open mode cannot be specified when the IC is destroyed, it is important to take physical safety measures such as fusing if a special mode in excess of absolute rating limits is to be implemented. GND potential Make sure the potential for the GND pin is always kept at the minimum, regardless of the operating mode. In addition, verify that the GND voltage is lower than the potential of all terminals except SW, PGND and GND in all conditions, including electric transient events.
(2)
(3) Thermal design Do not exceed the power dissipation (Pd) of the package specification rating under actual operation. Provide sufficient margin in the thermal design to account for the Pd expected in actual use. (4) Short-circuits between pins and incorrect mounting position When mounting the IC onto the set PCB, be extremely careful about the orientation and position of the IC. The IC may be destroyed if it is incorrectly positioned for mounting. Do not short-circuit between pins, or between a pin and the power supply or ground terminal. Note that introducing foreign matter in these paths will cause shorts and may damage the IC. (5) Operation in strong electromagnetic fields Use in strong electromagnetic fields may cause malfunctions. Use extreme caution with electromagnetic fields. (6) ASO (Area of Safe Operation) Do not exceed the maximum ASO parameter or the absolute maximum ratings of the output driver. (7) TSD (Thermal Shutdown) circuit This product is provided with a built-in thermal shutdown (TSD) circuit, which is activated when the IC chip temperature rises to the threshold value. In this case, TSD automatically latches output OFF. Output is restored when the EN block is activated again, or when UVLO is deactivated. Note that the TSD circuit is provided for the exclusive purpose shutting down the IC in the presence of extreme heat, and is not designed to protect the IC per se or guarantee performance when or after extreme heat conditions occur. Therefore, do not operate the IC with the expectation of continued use or subsequent operation once the TSD is activated. (8) GND wiring pattern When both a small-signal GND and high current GND are present, single-point grounding (at the standard point on the circuit set board) is recommended. This will separate the small-signal and high current patterns, and serves to ensure that the high current flow and wire impedance will not change the small-signal GND voltage. In the same way, care must be taken to avoid wiring pattern fluctuations in any connected external component GND. (9) Operation in supply voltage range Circuit functionality is guaranteed within the operating ambient temperature, as long as the operation is within the supply voltage range. The standard electrical characteristics cannot be guaranteed. However, any variation in these values will be small, as long as the operation is within the supply voltage range.
(10) The application schematic presented above is an example of recommended circuit layout. Although the circuit example is sound, actual circuit characteristics should be checked carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When switching noise is substantial and may impact the system, a low pass filter should be inserted between the Vcc and PVcc pins, and a Schottky barrier diode established between the SW and PGND pins.
REV. A
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(11) Overcurrent protection circuit/Output short protection circuit The overcurrent protection circuit is built into output, and functions as the current limit. Note that if the protection circuit operates more than a specified time period (when the output short-circuit protection circuit detects a load short or other similar state) the output will be latched OFF. Output is restored when the EN block is activated again, or when UVLO is deactivated. Although the protection circuits effectively prevent IC destruction under fault conditions, they should not be employed continuously.
(12) Selection of inductor Please use an inductor with a series resistance element (DCR) under 0.2. Note that use of a high DCR inductor will cause an inductor loss, resulting in decreased voltage output. Should this condition continue for a specified period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched OFF. When using an inductor over 0.2, be careful to ensure adequate margins for variation between eternal devices and this IC, including transient as well as static characteristics.
REV. A
Notice
Notes
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